题解 | #根据状态转移表实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
      input                A   ,
      input                clk ,
      input                rst_n,
 
      output   wire        Y   
);

parameter S0 = 2'b00,
          S1 = 2'b01,
          S2 = 2'b10,
          S3 = 2'b11;

reg [1:0] c_state , n_state;
reg Y_buff;

assign Y = Y_buff;

always@(posedge clk or negedge rst_n)begin
    if(!rst_n)
        c_state <= S0;
    else
        c_state <= n_state;
end

always@(*)begin
    n_state = c_state;
    case(c_state)
        S0:begin
            Y_buff = 1'b0;
            if(A)
                n_state = S3;
            else
                n_state = S1;
        end
        S1:begin
            Y_buff = 1'b0;
            if(A)
                n_state = S0;
            else
                n_state = S2;
        end
        S2:begin
            Y_buff = 1'b0;
            if(A)  
                n_state = S1;
            else
                n_state = S3;
        end
        S3:begin
            Y_buff = 1'b1;
            if(A)
                n_state = S2;
            else
                n_state = S0;
        end
    endcase
end

endmodule

两段式状态机很容易实现