题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
reg  [1:0] cnt;
wire  [10:0] out1;
wire  [13:0] out3;
wire  [13:0] out7;
wire  [13:0] out8;
//*************code***********//
always@(posedge clk or negedge rst)begin
    if(!rst) begin
        cnt <= 2'b0;
    end
    else begin
        cnt <= cnt + 1'b1;
    end
end

/* */
always@(posedge clk or negedge rst)begin
    if(!rst) begin
        input_grant <= 1'b0;
    end
    else begin
        if(cnt==0) input_grant <= 1'b1;
        else input_grant <= 1'b0;
    end
end
//
assign out1 = (cnt==0 && rst==1) ? {{3{1'b0}},d} : out1;
assign out3 = (rst==1) ? ((out1 << 1) + out1) : 14'd0;
assign out7 = (rst==1) ? ((out1 << 3) - out1) : 14'd0;
assign out8 = (rst==1) ? (out1 << 3) : 14'd0;
/*用下面时序逻辑的写法是很常见的思维，但是有个问题就是题目要求每个时钟输出一个数据，所以如果采用时序逻辑的话，需要两个clk才能输出。直接使用组合逻辑，算出四个值，在时钟计数下依次输出四个值，注意的是每隔四个时钟采样一次输入数据；左移需要考虑位扩展*/
// always@(posedge clk or negedge rst)begin
//     if (!rst)
//         out1 <= 11'd0;
//     else
//         out1 <= (cnt==0) ? {{3{1'b0}},d} : out1;
// end

// always@(posedge clk or negedge rst)begin
//     if(!rst) begin
//         out3 <= 14'd0;
//         out7 <= 14'd0;
//         out8 <= 14'd0;
//     end
//     else begin
//         out3 <= (out1 << 2) + out1;
//         out7 <= (out1 << 3) - out1;
//         out8 <= out1 << 3;
//     end
// end

always@(posedge clk or negedge rst)begin
    if (!rst)
        out <= 11'd0;
    else begin
        case(cnt)
        2'd0 : out <= out1;
        2'd1 : out <= out3[10:0];
        2'd2 : out <= out7[10:0];
        2'd3 : out <= out8[10:0];
        endcase
    end
end
//*************code***********//
endmodule