题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter A = 3'b000, B = 3'b001, C = 3'b010, D = 3'b011, E = 3'b100, F = 3'b101, G = 3'b110;
reg [2:0] cur_state, next_state;
wire [2:0] input_combination;
assign input_combination = {d3, d2, d1};
always @ (posedge clk or negedge rst) begin
	if(!rst) begin
		cur_state <= A;
	end
	else begin
		cur_state <= next_state;
	end
end
always @ (*) begin
	case(cur_state)
	A: begin
		case(input_combination)
		3'b001: next_state = B;
		3'b010: next_state = C;
		3'b100: next_state = G;
		default: next_state = next_state;
		endcase
	end
	B: begin
		case(input_combination)
		3'b001: next_state = C;
		3'b010: next_state = D;
		3'b100: next_state = E;
		default: next_state = next_state;
		endcase
	end
	C: begin
		case(input_combination)
		3'b001: next_state = D;
		3'b010: next_state = G;
		3'b100: next_state = F;
		default: next_state = next_state;
		endcase
	end
	default: next_state = A;
	endcase
end
always @ (posedge clk or rst) begin
	if(!rst) begin
		out1 <= 1'b0;
		out2 <= 2'b0;
	end
	else begin
		case(next_state)
		D: begin
			out1 <= 1'b1;
			out2 <= 2'b0;
		end
		E: begin
			out1 <= 1'b1;
			out2 <= 2'b10;
		end
		F: begin
			out1 <= 1'b1;
			out2 <= 2'b11;
		end
		G: begin
			out1 <= 1'b1;
			out2 <= 2'b01;
		end
		default: begin
			out1 <= 1'b0;
			out2 <= 2'b0;
		end
		endcase
	end
end
		

//*************code***********//
endmodule