题解 | #使用子模块实现三输入数的大小比较#
使用子模块实现三输入数的大小比较
https://www.nowcoder.com/practice/bfc9e2f37fe84c678f6fd04dbce0ad27?tpId=301&tqId=5000620&ru=%2Fpractice%2F1649582a755a4fabb9763d07e62a9752&qru=%2Fta%2Fverilog-start%2Fquestion-ranking&sourceUrl=%2Fexam%2Foj%3Fpage%3D1%26tab%3DVerilog%25E7%25AF%2587%26topicId%3D301
`timescale 1ns/1ns module main_mod( input clk, input rst_n, input [7:0]a, input [7:0]b, input [7:0]c, output [7:0]d ); wire [7:0] c_temp; reg [7:0] c_reg; always @(posedge clk or negedge rst_n) if(!rst_n) c_reg <= 8'd0; else c_reg <= c; sub_mod sub_mod_0 (clk, rst_n, a, b, c_temp); sub_mod sub_mod_1 (clk, rst_n, c_reg, c_temp, d); endmodule module sub_mod( input clk, input rst_n, input [7:0] a, input [7:0] b, output reg [7:0] c ); always @(posedge clk or negedge rst_n) if(!rst_n) c <= 8'd0; else c = (a <= b) ? a : b; endmodule
以我的经历，我的带教有十几年工作经验，做过运维、后端开发、web测试，现在是高级软测，是行走的避坑指南
