题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [15:0] temp;
reg [1:0] cnt_temp;
reg [3:0] cnt_out;
reg [127:0]	data_out_temp;
//向左移位存入data_out，设置计数器，确定已经接收到了足够的数据，用于确认输出
//若temp中有有效数据，则依次将temp和data_in移位存入data_out
//若data_in未全部被使用，则将剩余部分存入data_temp，设置计数器，记录temp中的有效位数
always@(posedge clk, negedge rst_n) begin
	if(!rst_n) cnt_out <= 4'd0;
	else begin
		if(valid_in) begin
			if(cnt_out == 4'd0) begin
				if(cnt_temp == 2'd1) cnt_out <= cnt_out + 4'd4;
				else if(cnt_temp == 2'd2) cnt_out <= cnt_out + 4'd5;
				else cnt_out <= cnt_out + 4'd3;
			end
			else if(cnt_out > 4'd12) cnt_out <= 4'd0;
			else cnt_out <= cnt_out + 4'd3;
		end
	end
end

always@(posedge clk, negedge rst_n) begin
	if(!rst_n) begin
		cnt_temp <= 4'd0;
		temp <= 16'd0;
	end
	else begin
		if(valid_in) begin
			case(cnt_out)
				4'd14:	begin cnt_temp <= 2'd1; temp[15:8] <= data_in[7:0]; end
				4'd15:	begin cnt_temp <= 2'd2; temp <= data_in[15:0]; end
				default:	begin cnt_temp <= 2'd0; temp <= 16'd0; end
			endcase
		end
	end
end

always@(posedge clk, negedge rst_n) begin
	if(!rst_n) data_out_temp <= 128'd0;
	else begin
		if(valid_in) begin
			if(cnt_out == 4'd0) begin
				if(cnt_temp == 2'd1) data_out_temp <= {data_out_temp[95:0],temp[15:8], data_in};
				else if(cnt_temp == 2'd2) data_out_temp <= {data_out_temp[87:0],temp, data_in};
				else data_out_temp <= {data_out_temp[103:0], data_in};
			end
			else if(cnt_out == 4'd14) begin
				data_out_temp <= {data_out_temp[111:0], data_in[23:8]};
			end
			else if(cnt_out == 4'd15) begin
				data_out_temp <= {data_out_temp[119:0], data_in[23:16]};
			end
			else data_out_temp <= {data_out_temp[103:0], data_in};
		end
	end
end

//当data_out存入足够的数据后，下一时刻valid_out拉高，保持一个时钟周期
always@(posedge clk, negedge rst_n) begin
	if(!rst_n) valid_out <= 1'b0;
	else begin
		if(valid_in && (cnt_out > 4'd12)) valid_out <= 1'b1;
		else valid_out <= 1'b0;
	end
end
always@(*) begin
	data_out = rst_n?(valid_out?data_out_temp:data_out):128'd0;
end
endmodule