题解 | #自动贩售机1#

`timescale 1ns/1ns
module seller1(
	input wire clk  ,
	input wire rst  ,
	input wire d1 ,
	input wire d2 ,
	input wire d3 ,
	
	output reg out1,
	output reg [1:0]out2
);
//*************code***********//
parameter s0=8'b00000001,
		  s1=8'b00000010,
		  s2=8'b00000100,
		  s3=8'b00001000,
		  s4=8'b00010000,
		  s5=8'b00100000,
		  s6=8'b01000000,
		  s7=8'b10000000;

		  reg [7:0]n_state;
		  reg [7:0]c_state;

		  wire [2:0]reg_d;
		  assign reg_d={d1,d2,d3};

		always@(posedge clk or negedge rst)
		if(!rst)
			c_state<=s0;
		else
			c_state<=n_state;

		always@(*) 
		case(c_state)
		s0:begin
			case(reg_d)
			3'b100:n_state=s1;
			3'b010:n_state=s2;
			3'b001:n_state=s4;
			default:n_state=n_state;
			endcase
		end 
		s1:begin
			case(reg_d)
			3'b100:n_state=s2;
			3'b010:n_state=s3;
			3'b001:n_state=s5;
			default:n_state=n_state;
			endcase
		end
		s2:begin
			case(reg_d)
			3'b100:n_state=s3;
			3'b010:n_state=s4;
			3'b001:n_state=s6;
			default:n_state=n_state;
			endcase
		end
		s3:n_state=s0;
		s4:n_state=s0;
		s5:n_state=s0;
		s6:n_state=s0;
		default:n_state=s0;
		endcase
		
		always@(posedge clk or negedge rst)
		if(!rst)begin
			out1<=0;
			out2<=0;
		end
		else begin
			case(n_state)
			s3:begin
				out1<=1;
				out2<=0;	
			end
			s4:begin
				out1<=1;
				out2<=1;	
			end
			s5:begin
				out1<=1;
				out2<=2;	
			end
			s6:begin
				out1<=1;
				out2<=3;	
			end
			default:begin
				out1<=0;
				out2<=0;	
			end
			endcase
		end


//*************code***********//
endmodule