题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);

wire [7:0] min0;
wire [7:0] min1;

min min_u0(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(b),
	.min(min0)
);

min min_u1(
	.clk(clk),
	.rst_n(rst_n),
	.a(a),
	.b(c),
	.min(min1)
);

min min_u2(
	.clk(clk),
	.rst_n(rst_n),
	.a(min0),
	.b(min1),
	.min(d)
);

endmodule

module min(
	input clk,
	input rst_n,
	input [7:0] a,
	input [7:0] b,
	output reg [7:0] min
);

always @( posedge clk or negedge rst_n )
begin
	if( !rst_n )
		min <= 8'h0;
	else
	begin
		if( a < b)
			min <= a;
		else
			min <= b;
	end
end

endmodule