题解 | #占空比50%的奇数分频#

`timescale 1ns/1ns

module odo_div_or
   (
    input    wire  rst ,
    input    wire  clk_in,
    output   wire  clk_out7
    );

//*************code***********//

    reg [3:0] cnt_p;
    always @(posedge clk_in or negedge rst) begin
        if (~rst) begin
            cnt_p <= 0;
        end else begin
            if (cnt_p == 6) begin
                cnt_p <= 0;
            end else begin
                cnt_p <= cnt_p + 1;
            end
        end
    end

    reg clk_p;
    always @(posedge clk_in or negedge rst) begin
        if (~rst) begin
            clk_p <= 0;
        end else begin
            if (cnt_p == 3 || cnt_p == 6) begin
                clk_p <= ~clk_p;
            end 
        end
    end

    reg [3:0] cnt_n;
    always @(negedge clk_in or negedge rst) begin
        if (~rst) begin
            cnt_n <= 0;
        end else begin
            if (cnt_n == 6) begin
                cnt_n <= 0;
            end else begin
                cnt_n <= cnt_n + 1;
            end
        end
    end

    reg clk_n;
    always @(negedge clk_in or negedge rst) begin
        if (~rst) begin
            clk_n <= 0;
        end else begin
            if (cnt_n == 3 || cnt_n == 6) begin
                clk_n <= ~clk_n;
            end 
        end
    end
    
    assign clk_out7 = clk_p | clk_n;

//*************code***********//
endmodule

时钟上升沿和下降沿分别采用一个周期为7的计数器，分别负责7时取反和3.5时取反。