题解 | #异步复位的串联T触发器#

`timescale 1ns/1ns
module Tff_2 (
input wire data, clk, rst,
output reg q  
);
//*************code***********//
    reg temp;
    always @(posedge clk or negedge rst) begin
        if (~rst) begin
            temp <= 0;
            q <= 0;
        end else begin
            if (data == 1) begin
                temp <= ~temp;
            end else begin
                temp <= temp;
            end
            if (temp == 1) begin
                q <= ~q;
            end else begin
                q <= q;
            end
        end
    end


//*************code***********//
endmodule