题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
// clk_a 时钟域的 data_en 寄存
reg data_en_a_reg;
always @ (posedge clk_a or negedge arstn) 
begin
    if( ~arstn ) begin
        data_en_a_reg <= 1'b0;
    end 
    else begin
        data_en_a_reg <= data_en;
    end 
end

// clk_a 时钟域的 data_in 寄存
reg [3:0] data_in_a_reg;
always @ (posedge clk_a or negedge arstn) 
begin
    if( ~arstn ) begin
        data_in_a_reg <= 4'b0;
    end 
    else begin
        data_in_a_reg <= data_in;
    end 
end

reg data_en_b_t;
reg data_en_b;
always @ (posedge clk_b or negedge brstn) 
begin
    if( ~brstn ) begin
        data_en_b_t <= 1'b0;
        data_en_b <= 1'b0;
    end 
    else begin
        data_en_b_t <= data_en_a_reg;
        data_en_b <= data_en_b_t;
    end 
end

always @ (posedge clk_b or negedge brstn) 
begin
    if( ~brstn ) begin
        dataout <= 4'b0;
    end 
    else begin
        if(data_en_b)
            dataout <= data_in_a_reg;
        else
            dataout <= dataout;
    end 
end
endmodule