题解 | #状态机与时钟分频#

`timescale 1ns/1ns

module huawei7(
	input wire clk  ,
	input wire rst  ,
	output reg clk_out
);

//*************code***********//
reg [2:0] counter;
always @(posedge clk or negedge rst) begin
	if(!rst)begin
		counter <= 0;
	end
	else if(counter == 3)begin
		counter <= 0;
	end
	else begin
		counter <= counter + 1;
	end
end
always @(posedge clk or negedge rst) begin
	if(!rst)begin
		clk_out <= 0;
	end
	else if(counter == 0)begin
		clk_out <= 1;
	end
	else begin
		clk_out <= 0;
	end
end
//*************code***********//
endmodule