题解 | #根据RTL图编写Verilog程序#
根据RTL图编写Verilog程序
https://www.nowcoder.com/practice/41a06522d8b242808c31a152bf948b5e
`timescale 1ns/1ns module RTL( input clk, input rst_n, input data_in, output reg data_out ); reg q1; always@(posedge clk,negedge rst_n) begin if(!rst_n) q1<=0; else q1<=data_in; end always@(posedge clk,negedge rst_n) begin if(!rst_n) data_out<=0; else data_out<=!q1&data_in; end endmodule
投递腾讯等公司7个岗位 >