题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg [2:0] state,nstate;
reg [2:0] s0=0,s1=1,s2=2,s3=3,s4=4;
always@(posedge clk or negedge rst_n)begin
	if(~rst_n) begin
		state<=s0;
		nstate<=s0;
	end
	else state<=nstate;
end

always@(*)begin
	case(state)
		s0:nstate=(data==0&&data_valid==1)?s1:s0;
		s1:begin
			if(data_valid==1)
				nstate=data==0?s1:s2;
			else nstate=s0;
			end
		s2:begin
			if(data_valid==1)
				nstate=data==0?s1:s3;
			else nstate=s0;
			end
		s3:begin
			if(data_valid==1)
				nstate=data==0?s4:s0;
			else nstate=s0;
			end
		s4:begin
			if(data_valid==1)
				nstate=data==0?s1:s2;
			else nstate=s0;
			end
		default:nstate=s0;
	endcase
end

// always@(posedge clk or negedge rst_n)begin
always@(*)begin
	if(~rst_n) 
		match=0;
	else match=state==s4?1:0;
end
endmodule

双输入，单输出，每个状态四个方向