题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

reg  [5:0] data_reg;
reg  [3:0] cnt;
reg		   flag;

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		cnt<=4'd0;
	end
	else begin
		cnt<=(cnt==4'd5)?4'd0:(cnt+4'd1);
	end
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		data_reg<=6'd0;
		flag<=1'b0;
	end
	else begin
		data_reg<={data_reg[4:0],data};
		flag<=1'b0;
		if(cnt==4'd5)begin
			flag<=1'b1;
		end
	end
end
always@(*)begin
	if(!rst_n)begin
		match<=1'b0;
		not_match<=1'b0;
	end
	else begin
		if(flag)begin
			match<=(data_reg==6'b011100)?1'b1:1'b0;
			not_match<=(data_reg==6'b011100)?1'b0:1'b01;
		end
		else begin
			match<=1'b0;
			not_match<=1'b0;
		end
	end

end
endmodule