题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//
reg[1:0] state= 2'b00;
wire input_grant_temp,out_temp;
reg[7:0] d_temp ;
always @(posedge clk or negedge rst)begin
    if(~rst)begin
        input_grant <= 0;
        out <= 0;
    end
    else begin
        case(state)
            2'b00: 
            begin 
                d_temp <= d;
                out <= d;
                input_grant <= 1;
                state <= 2'b01;
            end
            2'b01:
            begin 
                out <= (d_temp<<2) -d_temp;
                input_grant <= 0;
                state <= 2'b10;
            end
            2'b10: 
            begin
                out <= (d_temp<<3) - d_temp;
                input_grant <= 0;
                state <= 2'b11;
            end
            2'b11: 
            begin
                out = d_temp<<3;
                input_grant = 0;
                state <= 2'b00;
            end
        endcase
    end
end


//*************code***********//
endmodule