`timescale 1ns/1ns module multi_sel( input [7:0]d , input clk, input rst, output reg input_grant, output reg [10:0]out ); //*************code***********// reg[1:0] state= 2'b00; wire input_grant_temp,out_temp; reg[7:0] d_temp ; always @(posedge clk or negedge rst)begin if(~rst)begin input_grant <...
