题解 | #并串转换#

`timescale 1ns/1ns
module huawei5(
	input wire clk  ,
	input wire rst  ,
	input wire [3:0]d ,
	output wire valid_in ,
	output wire dout
	);

//*************code***********//

reg rst_reg;
reg [1:0] count;
reg [3:0] d_reg;
reg [1:0] valid_in_reg;

always @(posedge clk)
  rst_reg <= rst;

always @(posedge clk or negedge rst) begin
	if (~rst)
	  count <= 0;
	else if (rst_reg)
	  count <= (count == 2'b11) ? 0 : count + 1;
end

always @(posedge clk or negedge rst) begin
	if (~rst)
	  d_reg <= 0;
	else if (count == 2'b10)
	  d_reg <= d;
	else if ((count == 2'b11) || (|valid_in_reg))
	  d_reg<= {d_reg[2:0], 1'b0};
end

assign dout = d_reg[3];

always @(posedge clk or negedge rst) begin
	if (~rst)
	  valid_in_reg <= 0;
	else
	  valid_in_reg <= {valid_in_reg, valid_in};
end

assign valid_in = (count == 2'b11);

//*************code***********//

endmodule