题解 | #边沿检测#

`timescale 1ns/1ns
module edge_detect(
	input clk,
	input rst_n,
	input a,
	
	output reg rise,
	output reg down
);

reg a_pre;

always @(posedge clk or negedge rst_n) begin
	if (!rst_n) begin
		rise <= 0;
		down <= 0;
	end 
	else begin
		if (!a_pre & a)	rise <= 1; 
		else rise <= 0;
		if (a_pre & !a)	down <= 1;
		else down <= 0;
	end
	a_pre <= a;
end


endmodule