题解 | #任意奇数倍时钟分频#

`timescale 1ns/1ns

module clk_divider
    #(parameter dividor = 5)
( 	input clk_in,
	input rst_n,
	output clk_out
);
	wire clk_out;
    //奇数分频，上升沿,下降沿(n-1)/2 ，n-1
	localparam log_N = $clog2(dividor);//向上取整
	reg[log_N-1 : 0] cnt;//计数0-div-1
	reg clk_p,clk_n;

	always @(posedge clk_in or negedge rst_n)
		if(!rst_n)
			cnt<='d0;
		else if(cnt == dividor-1)
			cnt<='d0;
		else
			cnt<= cnt+1;
	
	always @(posedge clk_in or negedge rst_n)
		if(!rst_n)
			clk_p <= 1'b0;
		else if(cnt == (dividor -1)/2)
			clk_p <= 1'b1;
		else if(cnt == (dividor -1))
			clk_p <= 1'b0;
		else
			clk_p<= clk_p;

	always @(negedge clk_in or negedge rst_n)
		if(!rst_n)
			clk_n <= 1'b0;
		else if(cnt == (dividor -1)/2)
			clk_n <= 1'b1;
		else if(cnt == (dividor -1))
			clk_n <= 1'b0;
		else
			clk_n <= clk_n;


	assign clk_out = clk_p | clk_n;
endmodule