题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   	clk 		,   
	input 				   	rst_n		,
	input				    valid_in	,
	input	   [7:0]		data_in		,
 
 	output	reg				valid_out	,
	output  reg [15:0]		data_out
);

	reg [1:0] cnt;
	always @(posedge clk or negedge rst_n) 
	begin
		if(~rst_n)
			cnt <= 2'd0;
		else
			if(valid_in)
				cnt <= (cnt==2'd1)? 2'd0 : cnt+1'd1;
			else
				cnt <= cnt;
	end

	// valid_out
	always @(posedge clk or negedge rst_n) 
	begin
		if(~rst_n)
			valid_out <= 1'b0;
		else
			// 这里还是要注意一下，在判断valid_out时，判断条件要加上valid_in
			valid_out <= (cnt==2'd1)&&valid_in;
	end

	// data_reg
	reg [15:0] data_reg;
	always @(posedge clk or negedge rst_n) 
	begin
		if(~rst_n)
			data_reg <= 16'h0;
		else begin
			if(valid_in)
				data_reg <= {data_reg[7:0], data_in};
			else
				data_reg <= data_reg;
		end
	end

	// data_out
	always @( *) begin
		if(~rst_n)
			data_out = 'h0;
		else
			data_out = (valid_out)? data_reg : data_out;
	end

endmodule