题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);
reg	[1:0] q_current;
reg [1:0] q_next;
parameter IDLE = 0,
		  S1 = 1,
		  S2 = 2,
		  S3 = 3;
always@(posedge clk or negedge rst_n)
	if(!rst_n)begin
		q_current <= 2'b0;
		q_next <= 2'b0;
	end
	else begin
		q_current <= q_next;
	end


always@(*)begin
	if(!rst_n)begin
		match <= 1'b0;
	end
	else case(q_current)
		IDLE:begin
			if(data==0&&data_valid==1)begin
				q_next <= S1;
				match <= 1'b0;
			end
			else if(data==1&&data_valid==1)begin
				q_next <= IDLE;
				match <= 1'b0;
			end
			else begin
				q_next <= q_next;
				match <= 1'b0;
			end
		end
		S1:begin
			if(data==0&&data_valid==1)begin
				q_next <= S1;
				match <= 1'b0;
			end
			else if(data==1&&data_valid==1)begin
				q_next <= S2;
				match <= 1'b0;
			end
			else begin
				q_next <= q_next;
				match <= 1'b0;
			end
		end
		S2:begin
			if(data==0&&data_valid==1)begin
				q_next <= S1;
				match <= 1'b0;
			end
			else if(data==1&&data_valid==1)begin
				q_next <= S3;
				match <= 1'b0;
			end
			else begin
				q_next <= q_next;
				match <= 1'b0;
			end
		end
		S3:begin
			if(data==0&&data_valid==1)begin
				q_next <= IDLE;
				match <= 1'b1;
			end
			else if(data==1&&data_valid==1)begin
				q_next <= IDLE;
				match <= 1'b0;
			end
			else begin
				q_next <= q_next;
				match <= 1'b0;
			end
		end
		default:begin
			q_next <= IDLE;
			match <= 1'b0;
		end
	endcase
end

  
endmodule