题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0] min_1,min_2;
muxmin muxmin_1(.clk(clk),.rst_n(rst_n),.a(a),.b(b),.min_r(min_1));
muxmin muxmin_2(.clk(clk),.rst_n(rst_n),.a(a),.b(c),.min_r(min_2));
muxmin muxmin_3(.clk(clk),.rst_n(rst_n),.a(min_1),.b(min_2),.min_r(d));
endmodule

module muxmin(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	output reg [7:0]min_r
);
always@(posedge clk or negedge rst_n) begin
	if(!rst_n)
		min_r <= 0;
	else if (a > b) 
		min_r <= b;
	else
		min_r <= a;
end
endmodule