题解 | #多bit MUX同步器#

`timescale 1ns/1ns

module mux(
	input 				clk_a	, 
	input 				clk_b	,   
	input 				arstn	,
	input				brstn   ,
	input		[3:0]	data_in	,
	input               data_en ,

	output reg  [3:0] 	dataout
);
reg[3:0] data_temp ;//先在A时钟域缓存总是没错的
reg  data_en_a ;
always@(posedge clk_a or negedge arstn)begin
	if(~arstn)begin
		data_en_a <= 0;
		data_temp <= 4'b0 ;
	end
	else begin
		data_en_a <= data_en ;
		data_temp <= data_in ;
	end
end

//在b时钟域打2拍缓存后的使能信号完成传递
reg data_en_b0,data_en_b1;
always@(posedge clk_b or negedge brstn)begin
	if(~brstn)begin
		data_en_b0 <= 0;
		data_en_b1 <= 1;
	end
	else begin
		data_en_b0 <= data_en_a ;
		data_en_b1 <= data_en_b0;
	end
end
//mux选择
always@(posedge clk_b or negedge brstn)begin
	if(~brstn)begin
		dataout <= 0 ;
	end
	else begin
		dataout <= data_en_b1 ? data_temp : dataout ; //其他时候保持
	end
end

endmodule

DMUX 核心就是打拍缓存+选择器