题解 | #多位信号xnor#

`timescale 1ns/1ns

module top_module(
    input a, b, c, d, e,
	output [24:0] out
);

    wire [24:0] tmp1;
    wire [24:0] tmp2;
    assign tmp1 = {{5{a}}, {5{b}}, {5{c}}, {5{d}}, {5{e}}};
    assign tmp2 = {{5{a, b, c, d, e}}};

    assign out = tmp1 ~^ tmp2;
endmodule