题解 | #对信号按位操作#

`timescale 1ns/1ns

module top_module( 
    input [4:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and=in[4]&in[3]&in[2]&in[1]&in[0];
    assign out_or=in[4]|in[3]|in[2]|in[1]|in[0];
    assign out_xor=in[4]^in[3]^in[2]^in[1]^in[0];
endmodule