题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);
reg [119:0]  data_lock;
reg [3:0]    cnt;

always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt<= 0;
	end
	else if (valid_in) begin
		if(cnt=='d15)begin
			cnt<= 0;
		end
		else begin
		    cnt <= cnt +1'b1;
		end
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_lock <= 0;
		data_out <= 0;
	end
	else if(valid_in) begin
	 if (cnt=='d5) begin
        data_lock <= {data_lock[119:16], data_in[15:0]};
		data_out <= {data_lock,data_in[23:16]};
	
	end
	else if(cnt == 'd10) begin
		data_lock <={data_lock[119:8],data_in[7:0]};
		data_out <= {data_lock[111:0],data_in[23:8]};
	
	end
	else if(cnt == 'd15) begin
		data_lock <={data_lock[119:24],data_in[23:0]};
		data_out <= {data_lock[103:0],data_in};
	end
	else begin
		data_lock <= {data_lock[95:0],data_in};
	end
	end
end

always @(posedge clk or negedge rst_n)begin
	if(!rst_n) begin
		valid_out <= 0;
	end
	else if (valid_in&&(cnt=='d5))begin
		valid_out<= 1;
	end
	else if(valid_in&&(cnt=='d10))begin
		valid_out<=1;
	end
	else if(valid_in&&(cnt=='d15))begin
		valid_out<=1;
	end
	else begin
		valid_out<=0;
	end
end
endmodule