题解 | #使用子模块实现三输入数的大小比较#

`timescale 1ns/1ns
module main_mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,
	input [7:0]c,
	
	output [7:0]d
);
wire [7:0]d_r1,d_r2;
mod U1(.clk(clk),.rst_n(rst_n),.a(a),.b(b),.d(d_r1));
mod U2(.clk(clk),.rst_n(rst_n),.a(a),.b(c),.d(d_r2));
mod U3(.clk(clk),.rst_n(rst_n),.a(d_r1),.b(d_r2),.d(d));
endmodule

module mod(
	input clk,
	input rst_n,
	input [7:0]a,
	input [7:0]b,

	output reg[7:0]d
);
	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
			d<=0;
		else if(a>b)
			d<=b;
		else d<=a;
	end
endmodule