题解 | #根据状态转移图实现时序电路#

`timescale 1ns/1ns

module seq_circuit(
   input                C   ,
   input                clk ,
   input                rst_n,
 
   output   wire        Y   
);

reg [1:0]   cur_state,nxt_state;

always@(posedge clk or negedge rst_n)
    if(!rst_n)
        cur_state   <=  2'b00;
    else
        cur_state   <=  nxt_state;

always@(*)
    if(!rst_n)
        nxt_state   <=  2'b00;
    else    case(cur_state)
    2'b00:  nxt_state   <=  C? 2'b01:2'b00;
    2'b01:  nxt_state   <=  C? 2'b01:2'b11;
    2'b11:  nxt_state   <=  C? 2'b10:2'b11;
    2'b10:  nxt_state   <=  C? 2'b10:2'b00;
    default: nxt_state  <=  2'b00;
    endcase

assign Y = (nxt_state == 2'b10) | (cur_state == 2'b11);

endmodule