题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
); 

reg [7:0]data_reg;
reg [1:0]cnt;

//数据缓存寄存器更新
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_reg <= 0;
	else if(valid_in)
		data_reg <= data_in;
end

//计时器更新
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		cnt<=0;
	else if(valid_in)                                                        
		cnt <= (cnt==2'd2)?0:cnt+1;
end

//valid_out和data_out
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		valid_out <= 0;
	else 
		valid_out <= valid_in&&(cnt==1||cnt==2);
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_out <= 0;
	else if (cnt==1)
		data_out <= valid_in?{data_reg,data_in[7:4]}:data_out;
	else if (cnt==2)
		data_out <= valid_in?{data_reg[4:0],data_in[7:0]}:data_out;
	else
		data_out <= data_out;
end
endmodule

让人感觉很坑的一点是，题目中波形图给的不全。。。。。。。。。。。。