题解 | #输入序列连续的序列检测#

module sequence_detect(
	input clk,
	input rst_n,
	input a,
	output reg match
	);
  
reg [3:0] curr_state,next_state;

always @(posedge clk or negedge rst_n)		//状态
begin
	if(!rst_n)
		curr_state <= 4'b0;
	else 
		curr_state <= next_state;
end

always @(*)									
begin
	case (curr_state)
		4'd0: 
			next_state <= a ? 4'd0:4'd1; 
		4'd1:
			next_state <= a ? 4'd2:4'd1;
		4'd2:
			next_state <= a ? 4'd3:4'd1; //110001
		4'd3:
			next_state <= a ? 4'd4:4'd1;
		4'd4:
			next_state <= a ? 4'd0:4'd5;
		4'd5:
			next_state <= a ? 4'd0:4'd6;
		4'd6:
			next_state <= a ? 4'd0:4'd7;
		4'd7:  
			next_state <= a ? 4'd8:4'd0; 
		4'd8:  
			next_state <= a ? 4'd0:4'd1; 
		default:
			next_state <= 4'd0;
	endcase  		
end
  
always @(posedge clk or negedge rst_n)
begin
	if(!rst_n)
		match <= 1'b0;
	else if(curr_state == 4'd8)
		match <= 1'b1;
	else
		match <= 1'b0;
end
endmodule