题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				clk 		,   
	input				rst_n		,
	input				valid_in	,
	input	   [7:0]	data_in		,
 
 	output reg			valid_out	,
	output reg [15:0]	data_out
);

reg [7:0] data_in_reg;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		data_in_reg <= 8'd0;
	else
		data_in_reg <= valid_in ? data_in : data_in_reg;
end

reg flag;
always@(posedge clk or negedge rst_n)begin
	if(!rst_n)
		flag <= 1'b0;
	else
		flag <= valid_in ? ~flag : flag;
end

always@(posedge clk or negedge rst_n)begin
	if(!rst_n)begin
		valid_out <= 1'b0;
		data_out <= 16'd0;
	end
	else if(valid_in && flag)begin
		valid_out <= 1'b1;
		data_out <= {data_in_reg,data_in};
	end
	else begin
		valid_out <= 1'b0;
		data_out <= data_out;
	end
end

endmodule

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