题解 | 用8线-3线优先编码器实现16线-4线优先编码器

`timescale 1ns/1ns
module encoder_83(
   input      [7:0]       I   ,
   input                  EI  ,
   
   output wire [2:0]      Y   ,
   output wire            GS  ,
   output wire            EO    
);
assign Y[2] = EI & (I[7] | I[6] | I[5] | I[4]);
assign Y[1] = EI & (I[7] | I[6] | ~I[5]&~I[4]&I[3] | ~I[5]&~I[4]&I[2]);
assign Y[0] = EI & (I[7] | ~I[6]&I[5] | ~I[6]&~I[4]&I[3] | ~I[6]&~I[4]&~I[2]&I[1]);

assign EO = EI&~I[7]&~I[6]&~I[5]&~I[4]&~I[3]&~I[2]&~I[1]&~I[0];

assign GS = EI&(I[7] | I[6] | I[5] | I[4] | I[3] | I[2] | I[1] | I[0]);
//assign GS = EI&(| I);
         
endmodule


module encoder_164(
    input [15:0] A,
    input EI,
    output wire[3:0] L,
    output wire GS,
    output wire EO
); 

wire [2:0]Y_h;
wire [2:0]Y_l;

wire GS_h;
wire GS_l;

wire EO_h;
wire EO_l;

encoder_83 U1(
    .I(A[15:8]),
    .EI(EI),
    .Y(Y_h),
    .GS(GS_h),
    .EO(EO_h)
);

encoder_83 U2(
    .I(A[7:0]),
    .EI(EI),
    .Y(Y_l),
    .GS(GS_l),
    .EO(EO_l)
);
reg[3:0]L_tmp;
reg GS_tmp;
reg EO_tmp;

assign L=L_tmp;
assign GS = GS_tmp;
assign EO = EO_h&EO_l;

always@(*)begin
    if(GS_h)begin
        L_tmp={1'd1,{Y_h}};
        GS_tmp=GS_h;
        
    end
    else if(GS_l)begin
        L_tmp={1'd0,{Y_l}};
        GS_tmp=GS_l;
        
    end
    else begin
        L_tmp=0;
        GS_tmp=0;;
        EO_tmp=1;
    end
end
endmodule

注意一下EO得是&才能允许输出