题解 | #使用generate…for语句简化代码#
使用generate…for语句简化代码
https://www.nowcoder.com/practice/618cb8d16a2c4e87b9e305f6659efe40
`timescale 1ns/1ns
module gen_for_module(
input [7:0] data_in,
output [7:0] data_out
);
genvar i;
generate
for(i = 0;i<8;i = i+1)
begin: label1
assign data_out[i] = data_in[7-i];
end
endgenerate
endmodule
verilog for循环不能用i++