题解 | #数据累加输出#

`timescale 1ns/1ns

module valid_ready(
	input 				clk 		,   
	input 				rst_n		,
	input		[7:0]	data_in		,
	input				valid_a		,
	input	 			ready_b		,
 
 	output		 		ready_a		,
 	output	reg			valid_b		,
	output  reg [9:0] 	data_out
);


wire b;
assign ready_a = (cnt != 2'd0 || ready_b );  //输出 ready_a

reg [1:0] cnt ;
reg  cnt_flag ;
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt <= 'd0;
	end
	else if(valid_a && ready_a)
		cnt <= cnt + 'd1 ;
end

//输出 valid_b
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_b <= 0;
	end
	else if(valid_a && ready_a)
		valid_b <= cnt == 2'd3 ;
end

//输出 data_out
always@(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out <= 0;
	end
	else if(valid_a && ready_a)
		data_out <= (cnt == 'd0) ? data_in : data_in + data_out ;
end

endmodule