题解 | #数据串转并电路#

`timescale 1ns/1ns

module s_to_p(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_a		,
	input	 			data_a		,
 
 	output	reg 		ready_a		,
 	output	reg			valid_b		,
	output  reg [5:0] 	data_b
);
reg [2:0] seq_flag ;
reg [5:0]    seq    ;
always@(posedge clk or negedge rst_n)  begin
	if(!rst_n)    begin
		seq <= 0 ;
		seq_flag <= 0 ;
	end else if(valid_a) begin
    	seq <= {data_a, seq[5:1]};   //重点是这个
		if(seq_flag == 3'd5)  seq_flag <= 0;
		else seq_flag <= seq_flag + 1 ;
	end 

end

always@(posedge clk or negedge rst_n)  begin
	if(!rst_n)  begin
		data_b <= 0 ;
		valid_b <= 0 ;
		ready_a <= 0 ;
	end else if(seq_flag == 3'd5 ) begin 
		data_b <= {data_a, seq[5:1]} ;
		valid_b <= 1 ;
		ready_a <= 1 ;
	end else begin
		data_b <= data_b ;
		valid_b <= 0;
		ready_a <= 1;
	end
end



endmodule