题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(input clk,
                       input rst_n,
                       input data,
                       output reg match,
                       output reg not_match);
    
    parameter idle = 4'd0 ,
    S1 = 4'd1 , S2 = 4'd2, S3 = 4'd3 ,S4 = 4'd5 ,S5 = 4'd6 , S6 = 4'd7,
    C1 = 4'd8 , C2 = 4'd9, C3 = 4'd10,C4 = 4'd11,C5 = 4'd12, C6 = 4'd13;
    
    reg [3:0] state , next_state;
    
    always @(*) begin
        case (state) 
            idle : next_state = data ? C1 : S1;
            S1   : next_state = data ? S2 : C2;
            S2   : next_state = data ? S3 : C3 ;
            S3   : next_state = data ? S4 : C4 ;
            S4   : next_state = data ? C5 : S5;
            S5   : next_state = data ? C6 : S6;
            S6   : next_state = data ? C1 : S1;
            C1   : next_state = C2;
            C2   : next_state = C3;
            C3   : next_state = C4;
            C4   : next_state = C5;
            C5   : next_state = C6;
            C6   : next_state = data ? C1 : S1;
        endcase
    end
    
    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            state <= idle;
        end else begin
            state <= next_state;    
        end
    end
    
    always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            match <= 1'b0;
        end 
		else begin
            if(next_state == S6) begin
                match <= 1'b1;
            end 
			else begin
                match <= 1'b0;
            end
        end 
    end
    
       always @(posedge clk or negedge rst_n) begin
        if(!rst_n) begin
            not_match <= 1'b0;
        end 
		else begin
            if(next_state == C6) begin
                not_match <= 1'b1;
            end 
			else begin
                not_match <= 1'b0;
            end
        end 
    end
    
    
    
endmodule