题解 | #根据状态转移写状态机-三段式#

`timescale 1ns/1ns

module fsm1(
	input wire clk  ,
	input wire rst  ,
	input wire data ,
	output reg flag
);
//*************code***********//

reg [3:0] cur_state ;
reg [3:0] nex_state ;

parameter  S0  =   4'b0001 ,
           S1  =   4'b0010 ,
		   S2  =   4'b0100 ,
		   S3  =   4'b1000 ;

always@(posedge clk or negedge rst)begin
    if(!rst)
        cur_state <= S0         ;
	else 
	    cur_state <= nex_state  ;    
end


always@(*)begin
	case(cur_state)
	    S0: nex_state = (data == 1'b1)?S1:S0 ;
		S1: nex_state = (data == 1'b1)?S2:S1 ;
		S2: nex_state = (data == 1'b1)?S3:S2 ;
		S3: nex_state = (data == 1'b1)?S0:S3 ;
		default: nex_state = S0              ;
	endcase
end

always@(posedge clk or negedge rst)begin
	if(!rst)
	    flag <= 1'b0   ;
	else begin
		case(cur_state)
		    S3: begin
				if(data == 1 )
				     flag <= 1'b1 ;
				else
				     flag <=1'b0  ;
			end
			default: flag <= 1'b0 ;
		endcase
	end
end

//*************code***********//
endmodule

标准三段式