题解 | #位拆分与运算#

`timescale 1ns/1ns

module data_cal(
input clk,
input rst,
input [15:0]d,
input [1:0]sel,

output [4:0]out,
output validout
);
//*************code***********//
reg [4:0] out ;
reg validout ;
reg [15:0] d_reg ; //锁存输入
always@(posedge clk or negedge rst)begin
    if(!rst) begin 
        out <= 0;
        validout <= 0;
    end
    else 
        case(sel)
            2'b00:begin 
                d_reg <= d ;
                out <= 0 ;
                validout <= 0 ;
            end
            2'b01:begin
                out <= d_reg[3:0] + d_reg[7:4] ;
                validout <= 1 ;
            end
            2'b10:begin
                out <= d_reg[3:0] + d_reg[11:8] ;
                validout <= 1 ;
            end
            2'b11:begin
                out <= d_reg[3:0] + d_reg[15:12] ;
                validout <= 1 ;
            end
        endcase
end

//*************code***********//
endmodule