题解 | #序列发生器#

`timescale 1ns/1ns

module sequence_generator(
	input clk,
	input rst_n,
	output reg data
	);

reg [2:0] cnt;

always@(posedge clk, negedge rst_n)
if(rst_n==1'b0) cnt <= 'b0;
else if(cnt<5) cnt <= cnt+1'b1;
else cnt <= 'b0;

always@(posedge clk, negedge rst_n)
begin
if(rst_n==1'b0) data <= 1'b0;
else if(cnt==3'd0 || cnt==3'd1 || cnt==3'd3) data <= 1'b0;
else data <= 1'b1;
end
endmodule