题解 | #非整数倍数据位宽转换8to12#

`timescale 1ns/1ns

module width_8to12(
	input 				   clk 		,   
	input 			      rst_n		,
	input				      valid_in	,
	input	[7:0]			   data_in	,
 
 	output  reg			   valid_out,
	output  reg [11:0]   data_out
);
reg		[11:0]		data_pre;
reg		[2:0]		cnt;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		cnt <= 3'b0 ;
	end
	else if(valid_in) begin
	 	if(cnt == 3'd2 ) begin
		cnt <= 3'b0 ;
		end
		else  begin
		cnt <= cnt + 3'b1;
		end
	end
	else begin
		cnt <= cnt ;
	end

end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_pre <= 12'b0 ;
	end
	else if(valid_in) begin
		data_pre <= data_in;
	end
	else begin
		data_pre <= data_pre ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		data_out <= 12'b0 ;
	end
	else if(valid_in && cnt == 3'd1) begin
		data_out <= {data_pre[7:0],data_in[7:4]};
	end
	else if(valid_in && cnt == 3'd2) begin
		data_out <= {data_pre[3:0],data_in};
	end
	else begin
		data_out <= data_out ;
	end
end
always @(posedge clk or negedge rst_n) begin
	if(!rst_n) begin
		valid_out <= 1'b0 ;
	end
	else if(valid_in && cnt == 3'd1) begin
		valid_out <= 1'b1;
	end
	else if(valid_in && cnt == 3'd2) begin
		valid_out <= 1'b1;
	end
	else begin
		valid_out <= 1'b0;
	end
end
endmodule