题解 | #非整数倍数据位宽转换24to128#

`timescale 1ns/1ns

module width_24to128(
	input 				clk 		,   
	input 				rst_n		,
	input				valid_in	,
	input	[23:0]		data_in		,
 
 	output	reg			valid_out	,
	output  reg [127:0]	data_out
);

reg[3:0] cnt;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		cnt <= 4'b0;
	else begin
		cnt <= ~valid_in?cnt:cnt+1'b1;
	end
end

reg[127:0] data_lock;
always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		data_lock <= 128'd0;
	else begin
		data_lock <= valid_in?{data_lock[103:0],data_in}:data_lock;
	end
end

always @(posedge clk or negedge rst_n) begin
	if(!rst_n)
		valid_out <= 1'b0;
	else begin
		if((cnt==5||cnt==10||cnt==15)&&(valid_in))
		 	valid_out <= 1'b1; 
		else
			valid_out <= 1'b0;
	end
end

always @(posedge clk  or negedge rst_n) begin
	if(!rst_n)
		data_out <= 128'b0;
	else if(cnt == 5)
		data_out <= valid_in?{data_lock[119:0],data_in[23:16]}:data_out;
	else if(cnt == 10)
		data_out <= valid_in?{data_lock[111:0],data_in[23:8]}:data_out;
	else if(cnt == 15)
		data_out <= valid_in?{data_lock[103:0],data_in[23:0]}:data_out;
	else
		data_out <= data_out;
end
endmodule