题解 | #输入序列不连续的序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	input data_valid,
	output reg match
	);

reg [3:0] datareg;

always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			begin
				datareg <= 0;
			end
		else
			begin
				if(data_valid)
					datareg <= {datareg[2:0],data};
				else
					datareg <= datareg;
			end
	end

always @(posedge clk or negedge rst_n)
	begin
		if(~rst_n)
			begin
				match <= 0;
			end
		else
			begin
				if(datareg == 3'b011 && data ==0 && data_valid)
					match <= 1;
				else
					match <= 0;
			end
	end

endmodule