`timescale 1ns/1ns module fsm1( input wire clk , input wire rst , input wire data , output reg flag ); parameter s0 = 'd0,s1 = 'd1,s2 = 'd2, s3 = 'd3; reg [2:0] state,next_state; //*************code***********// always @(posedge clk or negedge rst) begin if(~rst) begin state <= s0; end else begin...
