题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);

	reg [2:0] count;
	reg [5:0] a_reg;

	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		begin
			count <= 3'd0;
			a_reg <= 6'd0;
		end
		else if (count == 3'd5)
		begin
			count <= 3'd0;
			a_reg <= 6'd0;
		end
		else 
		begin
			count <= count + 1'd1;
			a_reg[5-count] <= data;
		end
	end



	always@(posedge clk or negedge rst_n)begin
		if(!rst_n)
		begin
			match <= 1'b0;
			not_match <= 1'b0;
		end
		else if ((count == 3'd5) && (a_reg == 6'b011100))
			begin
			match <= 1'b1;
			not_match <= 1'b0;
			end
		else if (count == 3'd5)
			begin
			not_match <= 1'b1;
			match <= 1'b0;
			end
		else 
		begin
			match <=1'b0;
			not_match <= 1'b0;
		end
	end
endmodule