题解 | #无占空比要去的奇数分频#

`timescale 1ns/1ns

module odd_div (    
    input     wire rst ,
    input     wire clk_in,
    output    wire clk_out5
);
//*************code***********//

reg[2:0]cnt;
reg out;

always@(posedge clk_in or negedge rst)
begin
if(!rst)
begin
cnt=3'd0;
end
else
begin
cnt= (cnt==3'd5)?3'd1:cnt+3'd1;
end
end
always@(*)
begin
if(!rst)
begin
out = 1'b0;
end
else if(cnt==1||cnt==3)
begin
out=~out;
end
end
assign clk_out5=out;
//*************code***********//
endmodule