题解 | #移位运算与乘法#

`timescale 1ns/1ns
module multi_sel(
input [7:0]d ,
input clk,
input rst,
output reg input_grant,
output reg [10:0]out
);
//*************code***********//

    wire [10:0] d3, d7, d8;
    reg [1:0] counter;
    reg [10:0] d1;
    
    always @ (posedge clk, negedge rst) begin
        if (!rst) begin 
            counter <= 2'b0;
            out <= 11'b0;
            input_grant <= 1'b0;
        end
        else begin
            counter <= counter + 1;
            
            case (counter) 
                0: begin
                    d1 <= d;
                    out <= d;
                    input_grant <= 1'b1;
                end
                1: begin
                    out <= (d1 << 2) - d1;
                    input_grant <= 1'b0;
                end
                2: begin
                    out <= (d1 << 3) - d1;
                    input_grant <= 1'b0;
                end
                3: begin
                    out <= (d1 << 3);
                    input_grant <= 1'b0;
                end 
            endcase
        end
    end


//*************code***********//
endmodule