题解 | #优先编码器电路①#

`timescale 1ns/1ns

module encoder_0(
   input      [8:0]         I_n   ,
   
   output reg [3:0]         Y_n   
);

always@(*) 
    begin
        if(&I_n == 1'b1)   Y_n = 4'b1111;
        else if(I_n[8] == 1'b0) Y_n = 4'b0110;
        else if(I_n[8:7] == 2'b10) Y_n = 4'b0111;
        else if(I_n[8:6] == 3'b110) Y_n = 4'b1000;
        else if(I_n[8:5] == 4'b1110) Y_n = 4'b1001;
        else if(I_n[8:4] == 5'b11110) Y_n = 4'b1010;
        else if(I_n[8:3] == 6'b111110) Y_n = 4'b1011;
        else if(I_n[8:2] == 7'b1111110) Y_n = 4'b1100;
        else if(I_n[8:1] == 8'b11111110) Y_n = 4'b1101;
        else if(I_n[8:0] == 9'b111111110) Y_n = 4'b1110;
        else Y_n = 4'b0000;
    end
endmodule