题解 | #RAM的简单实现#

`timescale 1ns/1ns
module ram_mod(
	input clk,
	input rst_n,
	
	input write_en,
	input [7:0]write_addr,
	input [3:0]write_data,
	
	input read_en,
	input [7:0]read_addr,
	output reg [3:0]read_data
);

reg [3:0] ram [0:7];
integer i;

always@(posedge clk,negedge rst_n)
    begin
        if(rst_n==1'b0) begin
            for(i=0;i<=7;i=i+1)
                ram[i] <= 0;
        end
        else if(write_en == 1'b1) ram[write_addr] <= write_data;
    end


always@(*)
    begin
        if(rst_n==1'b0) begin
			read_data = 4'd0;
        end
		else if(read_en == 1'b1)  read_data = ram[read_addr];
    end
	
endmodule