题解 | #不重叠序列检测#

`timescale 1ns/1ns
module sequence_detect(
	input clk,
	input rst_n,
	input data,
	output reg match,
	output reg not_match
	);
	reg integer cnt;
	reg [5:0]comp;
	always @(posedge clk or negedge rst_n)begin
		if(~rst_n)begin
			cnt<=0;
			match<=0;
			not_match<=0;
		end
			else if(cnt==5)begin
			cnt<=0;
			end
			else cnt<=cnt+1;
		end
	always @(posedge clk or negedge rst_n)begin
		if(~rst_n)begin
			comp<=6'b0;
		end
		else comp[cnt]<=data;
	end

	always@(posedge clk or negedge rst_n)begin
		match<=((comp==6'b001110)&(cnt==5))?1:0;
		not_match<=(~(comp==6'b001110)&(cnt==5))?1:0;
	end
	
endmodule