题解 | #整数倍数据位宽转换8to16#

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);

	reg [7:0] data_temp;
	reg flag;

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_temp <= 8'd0;
		else if(valid_in)
			data_temp <= data_in;
		else
			data_temp <= data_temp;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			flag <= 1'b0;
		else if(valid_in)
			flag <= ~flag;		
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			data_out <= 16'd0;
		else if(valid_in && flag == 1'b1)
			data_out <= {data_temp,data_in};
		else
			data_out <= data_out;
	end

	always @(posedge clk or negedge rst_n) begin
		if(rst_n == 1'b0)
			valid_out <= 1'b0;
		else if(valid_in && flag == 1'b1)
			valid_out <= 1'b1;
		else
			valid_out <= 1'b0;
	end





endmodule